1. Field of the Invention
This invention relates generally to the field of semiconductor processing; and more specifically to the field of polishing methods and apparatus for planarizing thin films formed over a semiconductor substrate.
2. Discussion of the Related Art
In semiconductor device manufacturing of very large scale integrated (VLSI) circuits, extremely small electronic devices are formed in separate dies on a thin, flat semiconductor wafer. In general, various materials which are either conductive, insulating, or semiconducting are utilized in the fabrication of integrated circuitry on semiconductor wafers. These materials are patterned, doped with impurities, or deposited in layers by various processes to form integrated circuits. VLSI integrated circuits include patterned metal layers which are generally covered with dielectric materials, such as oxide, followed by a subsequent metalization, etc. The semiconductor wafers thus contain metalization layers and interlevel dielectrics.
Increasing circuitry miniaturization and a corresponding increase in density has resulted in a high degree of varying topography being created on an outer wafer surface during fabrication. It is often necessary to planarize a wafer surface having varying topography to provide a substantially flat planar surface. One such planarization process known in the art is chemical-mechanical polishing (CMP).
Chemical mechanical polishing or planarization has been widely used in the semiconductor industry for smoothing, polishing or planarizing coating or layers on the surface of semiconductor wafers. This process has been used to achieve the planarization, the controlled reduction in thickness, or even the complete removal of such layers which may include, for example, an oxide on the surface of the semiconductor wafer. Apparatus for such chemical mechanical polishing process is well known and used in the semiconductor industry and is currently commercially available.
Briefly, the chemical mechanical polishing process requires that a workpiece be held, with a desired coated surface face down, on a polishing pad supported on a rotating table, in the presence of an abrasive slurry. A chemical mechanical polishing machine can include a single rotating polishing plate having a polishing pad thereon and a smaller diameter rotating wafer carrier to which a wafer (or wafers) is (are) mounted. The wafer carrier is held above the polishing plate, either in a stationary fixed position or oscillating back and forth in a predetermined path in a horizontal plane, while both polishing plate and wafer carrier are rotated about their respective center axes. A slurry, consisting of an abrasive suspension with or without an etching reagent, is fed onto the polishing pad of the polishing plate during polishing of the wafer. The slurry, also referred to as a carrier liquid, can be selected to include an etchant for the coating being planarized and for not substantially attacking other materials involved in the process. The slurry is further fed between the polishing pad and the wafer being polished to polish and flush away the material removed from the semiconductor wafer.
Planarization of dielectric films using a CMP process requires varying properties for polishing pads. Soft polishing pads generally result in good global planarization (i.e., planarization across the wafer or substrate being polished) but are not very good at achieving local planarization (i.e., planarization across a single chip region on the wafer or substrate). On the other hand, hard polishing pads are very good at achieving local planarization but are not very good at achieving global planarization.
Several methods have been disclosed for achieving both local and global planarization. Such methods include the stacking of hard/soft polishing pads, placement of features of varied height on the polishing surface of the polishing pad, hard/soft regions, and grooves. With respect to the latter methods, the methods are implemented on a polishing side of the polishing pad.
In addition, with respect to CMP apparatus, polishing pad conditioning is known for providing a desired conditioning of a polishing pad during a polishing process. That is, polishing pad conditioning is used during the CMP process to provide a clean, fresh, polish surface after each wafer is planarized to a desired amount. The CMP process and polishing pad conditioning however result in a thinning of the polishing pad. For example, the thinning is in part a result of an abrasive action of a conditioning material.
Polishing pad end-of-life (EOL) can generally be indicated, for example, in one of several ways. That is, using process quality including, for example, measures of polishing uniformity, polishing rate, and polishing defects can be one method of providing an indication of polishing pad EOL. Another method may include polishing until a failure of either the pad or process, due to a thinning of the polishing pad. With advances in CMP polishing pad conditioning technology, process quality generally very good until the pad is too thin for continued safe use. In many cases a wafer limit (corresponding to a maximum safe number of wafers to be polished with a particular polishing pad, before pad EOL) is placed on pad life to insure that a particular pad is not used until it is too thin, i.e., beyond its usable life. A polishing pad wear is thus not well characterized with CMP apparatus and tools currently known in the art.
In addition, there are some conditions where a polish pad may wear unevenly which can result in poor polishing quality. Techniques to measure pad wear are time consuming and labor intensive involving topographic measurement of the pad's flatness.
It would thus be desirable to provide an improved polishing pad and polishing pad wear indicator for overcoming the problems as discussed herein above.